Suppose you're designing a paged memory system for an embedded device. A memory access on this...

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Suppose you're designing a paged memory system for an embedded device. A memory access on this system takes 20μs, and a TLB search takes 5μs. Fractions may be left unsimplified. CPU Virtual Address MMU TLB Physical Memory Page Table Physical Address a.) Suppose a memory access hits in the TLB, how long does the data take to get back to the CPU? b.) Suppose a memory access misses in the TLB, how long does the data take to get back to the CPU? c.) What is the average memory access time with a 50% hit rate? d.) What do you think would be the better improvement? Having a TLB hit rate of 100% or reducing the memory access time to 15µs? Why? Suppose you're designing a paged memory system for an embedded device. A memory access on this system takes 20μs, and a TLB search takes 5μs. Fractions may be left unsimplified. CPU Virtual Address MMU TLB Physical Memory Page Table Physical Address a.) Suppose a memory access hits in the TLB, how long does the data take to get back to the CPU? b.) Suppose a memory access misses in the TLB, how long does the data take to get back to the CPU? c.) What is the average memory access time with a 50% hit rate? d.) What do you think would be the better improvement? Having a TLB hit rate of 100% or reducing the memory access time to 15µs? Why?