SWITCHING CIRCUIT AND LOGIC DESIGN

Problem 9: (18 points) Expansion Let Boolean function F(a,b,c,d) = m(0.2,8,9,12,13,15) Assume that d is the least significant bit, so a'b'c'd correspond to minterm m. (a) (6%) Perform Shannon expansion on F with respect to input b. That means, write the minterm expansion of H and G such that: F = Hb+Gb'. (b) (6%) Draw a design to realize F using the results of part (a). Suppose you are given a 3-8 line decoder (inverted outputs), some NAND gates, and a 2-to-1 multiplexer. Suppose constants (like 0, 1) and complemented inputs (like b') are provided. (C) (6%) Suppose you are given a 5-input PLA (Programmable Logic Array). Can you implement function F by using this PLA? If so, please fill in the PLA table. It is not needed to draw the PLA internal connection. If not, please explain. (There is a PLA table example in next page. You can reference it.) Inputs Product Term Output F a b d For example, there is a 5-input PLA with the implementation of function F-a'b'+be. Product Inputs Output Term b d F a'b' 0 0 1 be 1 1 1 a C