[SystemC]

Problem 2. Write a SystemC model (write h and cpp) for a synchronous sequence detector. The detector has the following ports: Data in: input bit is synchronized with the rising edge of the clock Clock: Input clock Outl: generates 1 if "110" is detected Out2: generates 1 if sequence (3 bits) is equal to the internal bit counter. Internal 3-bit counter is incremented by 1 on the rising edge of the clock. Assume the counter goes from 000 to 111, and repeats from 000. Problem 2. Write a SystemC model (write h and cpp) for a synchronous sequence detector. The detector has the following ports: Data in: input bit is synchronized with the rising edge of the clock Clock: Input clock Outl: generates 1 if "110" is detected Out2: generates 1 if sequence (3 bits) is equal to the internal bit counter. Internal 3-bit counter is incremented by 1 on the rising edge of the clock. Assume the counter goes from 000 to 111, and repeats from 000