Table $1-$ ALU Truth Table

Step $1-$ Creating and Compiling the Project with Quatrus II Verilog

Computer the values of outputs $(,$ and $f0$ for various operations shown Table $1$ below and complete Table $1.$ Draw the Circuit Diagram. Write the Verilog code. You may consider using the sample Verilog code below:

Sample Verilog code using case statement is shown below:

$//$ ALU

module alu$($s$,$ A$,$ B$,$ F$)$;

input $[2$:$0]S$;

input $[3$:$0]A,B$;

output reg $[3$:$0]F$;

always @$(S,A,B)$

case $(S)0$:$F=4\text{'}$b$0000$;