Take Data input 8 for 4 bit Universal Shift Register (74LS194) and enter the output values that will occur for the given inputs in the table. (Please assume that the data remains constant at the entrance) Outputs Clear Clock QA QB Qc Qp D d Mode S1 SO H H H L H L L L L 1 1 1 a X X II I Inputs Serial Left Right X X H X L H L Parallel B C X b x x X X X X X X X X x x x Qon L L L L QAD Qco QDO b d H Qan Qen L Qan Qen Qon H Qen Och L QAD Q X X X X X Qen 1 1 Ocn Opn Qon H H Veri Girii Kontrol Girileri IKIS Clock A Clear si so Serial Serial Left Right QA QB QC QD 1 1 1 0 0 2 0 0 0 1 1 3 1 1 1 1 1 4 1 1 1 5 1 1 0 1 1 6 1 1 e 1 0 7 1 1 0 1 1 8 1 1 0 1 0 9 1 0 0 0 1 10 1 0 1 0 0 11 1 0 1 1 0 12 0 0 0 1 1 13 1 1 1 1 1 Take Data input 8 for 4 bit Universal Shift Register (74LS194) and enter the output values that will occur for the given inputs in the table. (Please assume that the data remains constant at the entrance) Outputs Clear Clock QA QB Qc Qp D d Mode S1 SO H H H L H L L L L 1 1 1 a X X II I Inputs Serial Left Right X X H X L H L Parallel B C X b x x X X X X X X X X x x x Qon L L L L QAD Qco QDO b d H Qan Qen L Qan Qen Qon H Qen Och L QAD Q X X X X X Qen 1 1 Ocn Opn Qon H H Veri Girii Kontrol Girileri IKIS Clock A Clear si so Serial Serial Left Right QA QB QC QD 1 1 1 0 0 2 0 0 0 1 1 3 1 1 1 1 1 4 1 1 1 5 1 1 0 1 1 6 1 1 e 1 0 7 1 1 0 1 1 8 1 1 0 1 0 9 1 0 0 0 1 10 1 0 1 0 0 11 1 0 1 1 0 12 0 0 0 1 1 13 1 1 1 1 1