Tania Architecture, a RISC computer, has separate IM and DM$.$ This architecture supports $100$ different instructions of fixed$-$length opcodes.

Here are the configurations for the memories:

Instruction Memory: $4$M $16,$ implemented using medium speed RAM of $256k8$

Data Memory: $128M32,$ implemented using faster speed RAM of $256k8$

Note: Your answers for all questions should be just a number. But you can certainly add explanations.

How many bytes is each Instruction word?

How many bytes is each data word?

If each instruction is $4$ bytes, how many memory locations will each instruction occupy?

How many chips are needed to implement the IM$?$

How many bits is the opcode for this ISA?

How many bits is the memory address for the DM$?$

The inventor wants to add a new instruction to the ISA: This instruction supports $1$ memory address for data $($answer from $6)+1$ signed integer between $-64$ and $63.$ What is the minimum size of this instruction?