Task 1: 1s or 2s complement

It is convenient how similar the 1s and 2s complement operations are. In both cases, each of the bits are individually complemented. And then that complemented result either has 0 or 1 added to it. Lets take advantage of this similarity.

Your task is to build a circuit that accepts a 4-bit input (so, 4 switches on the breadboard) and uses a select switch to perform either the 1s complement or 2s complement operation. Only two chips are needed for this. The first holds a type of gate that can do the complementing (hmmm what gate could that be?). The second must perform the addition of either 0 or 1.

There are a variety of options to achieve the addition, but we will be using a 4-bit adder (IC 74_283). Note the slightly strange naming of the ports: the weights of bits [A4, A3, A2, A1] are [8, 4, 2, 1] and C0 (the carry-in) has a weight of 1.

On this adder, one set of inputs should be the 4 complemented bits from the previous chip. The other set of inputs should be either:

0000 (for 1s complement, where we add 0), or

0001 (for 2s complement, where we add 1)

The select switch is the input that determines whether the circuit is adding 0 or 1 (so, where do you think the select switch should connect to the adder?).

In LogicWorks, use the chip schematics to simulate and test your design.

In report:

Describe the objective. In the process, define the 1s and 2s complement operations.

Describe and illustrate your design process (note that a truth table and a gate circuit probably arent necessary here)

Screenshots from LogicWorks of the schematic.

Task 2: No change or Sign-magnitude

It is also convenient how similar positive and negative numbers are in sign-magnitude form (the only difference is the leading bit). In this task, you will build a logic circuit that allows you to choose to output either a positive or negative 4-bit number in sign-magnitude form.

To make this choice, take advantage of a special interpretation of the Exclusive-OR gate. In Figure 1, consider input D as the data bit that you might want to invert and C as the control signal that determines whether you invert or not. If C=1, then you have selected Invert, and Y=D. If C=0, then you have selected No Change, and Y=D.

Figure 1: Interpreting the XOR gate as a controlled complementor. When C=1, Y=D'. When C=0, Y=D

Based on this concept, design and build a very simple circuit with 4 input data switches, 1 select switch, and 4 output signals. If the select switch is Low, then there should be no change between input and output. If the select switch is High, then the output should be the negated version of the input (in sign-magnitude form).

How simple is this circuit? Three wires will feed directly from inputs to outputs and only a single gate on a single chip needs to be used.

In LogicWorks, use the chip schematics to simulate and test your design.

In report:

Describe the objective. In the process, define sign-magnitude form.

Explain the use of the XOR gate as a controlled inverter

Two screenshots demonstrating the +6₁₀ with no change and one showing +6₁₀ negated.

Task 3: 4 options

Now your task is to combine what you did in Tasks 1 and 2 to build a circuit that has four modes, determined by two select switches (S₁, S₀):

(0,0) no change

(0,1) negate input in sign-magnitude form

(1,0) negate input in 1s complement form

(1,1) negate input in 2s complement form

Notice in this scheme that the S₁ value determines which general group is selected (Task 1 or Task 2 functions) and the S₀ value determines which function within those groups is selected (1s comp vs. 2s comp; No change vs. Sign-Magnitude). Therefore, the S₀ switch serves the same purpose as the individual select switch already used in both Task 1 and Task 2.

But that S₁ value needs a new device to allow it to select. That new device, unsurprisingly, is a data selector (or multiplexer, or mux). The mux IC available in our lab is the 74_157, which performs selection between two 4-bit numbers.

Looking at the device symbol:

This mux should always be enabled, so what logic value should be passed to the EN port?

When SEL=1, the input bits labeled with a 1 (such as D₁) are those that make it to the corresponding output bit (such as Q_D)

When SEL=0, the input bits labeled with a 0 are selected

Knowing this (and the mode definitions), you have two big questions to answer:

What should be connected to the 0 inputs (the outputs from Task 1 or Task 2)?

Which select switch (S₁ or S₀) should be connected to the SEL input?

In LogicWorks, use the chip schematics to simulate and test your design.

In report:

Clearly define the available modes

Describe and illustrate your design process

Four screenshots showing one for each select mode, given a data input of +3.

Discuss the value of multi-functional circuits

Discuss the value of a mux

A different design could be made here that uses three muxes to select between the four options. In that case, your select switches would connect only to the SEL ports on the various muxes. What shortcuts did you take to avoid that lengthier design? Can you always rely on shortcuts like this? What are the advantages/disadvantages of using those shortcuts? (possible topics: design time, build time, time-space continuum, propagation delays, understandability, cost)

Report requirements

Cover page. Include lab assignment number, title, date, course name, authors name

Introduction

Provide context. Assume the reader is not in this class and doesnt have this lab handout in front of them. What background information do they need to understand what you are about to discuss?

Define objectives. What did you build? Briefly describe the various circuits made and their purpose.

Design section for each requested task. Specific items required are listed under the tasks above.

Conclusion

Discuss applications. How might your circuits be useful?

Provide takeaways. What skills or knowledge was gained, both in regards to concepts and to practically using physical equipment or the simulator?