Question: Task 1 : Draw the state transition graph of the following circuit. Write a synthesizable model A in Systemverilog for the state transition graph. Task

Task 1: Draw the state transition graph of the following circuit. Write a synthesizable model A in Systemverilog for the state transition graph.
Task 2: Use DC to synthesize the model A to get a circuit B. Draw the obtained circuit B.
1
Task 1: Draw the state transition graph of the following circuit.

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