Task $2$:

A deMUX is performs basically the opposite operation than a mUX does. It is a combinational logic circuit

designed to switch one common input line to one of several separate output lines based on the select lines.

Source: Geeks for Geeks

At the end of unit $1$ we saw multiple ways we can implement a $1-$bit full adder. Remember, the truth table of a

full adder looks like follows:

We saw that the Sum and Carry outputs can be represented by the following expressions:

$S=x^{\text{'}}{Y}^{\text{'}}{C}_{in}+x^{\text{'}}Y{C}_{in}^{\text{'}}+xY{C}_{in}+x{Y}^{\text{'}}{C}_{in}$

$S=xo+Yo+C_{in}$

$C_{\text{o}\text{u}\text{t}}=xY+x{C}_{in}+Y{C}_{in}$

$C_{\text{o}\text{u}\text{t}}=xY+C_{in}(xo+Y)$

OR using the sum of minterm representation we saw in lecture:

$S((A),(B),C_{in})={\displaystyle \underset{?}{\overset{?}{}}}(1,2,4,7)$

Cout$(A,B,$Cin$)={\displaystyle \underset{?}{\overset{?}{}}}(3,5,6,7)$

For this task you are asked to do the following:

Show the implementation of the sum $($ S $)$ and the carry $(C_{\text{o}\text{u}\text{t}})$ outputs of a full$-$adder $(FA)$ using one $3-8$

Decoder and two OR$-$gates. Make sure you show all your work

Now repeat the exercise, but this time use an $1-8$ deMUX. Again, make sure you show all your work.

Last repeat the exercise, but this time use $28-1$ MUXes. Again, make sure you show all your work.

Extra Credit $(2$ points$)$: Repeat task $3,$ this time use $24-1$ MUXes instead. Make sure you show all your work.