Task 2: S-R Latch with enable (10 points) An S-R latch with enable operates according to the following function table. ON 001 last last ON 011 0 101 1 It can be built based on a S'-R' Latch. Write a VHDL program to implement the S- R Latch with Enable using structural design. Please adopt the following entity declaration. entity ar latch en is Ports in STD LOGIC: R in STD LOGIC C in STD LOGIC; Q: out STD LOGIC: ON: out STD LOGIC); end ar latch en: 31 Page Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, signal values, and the time. '0''' 10' 10' Requirement(s): In your VHDL implementation (1) Please follow the structural design method; (2) Make use of the module(s) you implemented before. Task 3: D-Latch (10 points) Build a D latch in Xilinx according to the following function table. C D QN 10 1 1 1 0x last Q last QN The D latch can be built based on an S-R Latch with Enable. Write a VHDL program to implement the D latch using structural design. Please adopt the following entity declaration. entity d latch is Port (C in D STD_LOGIC; in STD LOGIC; Q: out STD_LOGIC; QN: out STD LOGIC); end d_latch; 5| Page Write a test-bench program and run simulations to validate your design. Use the given test cases in your test-bench program. Pay attention to the signal names, 50 wait for 5 51 54 55 56 57 58 wait for 50 d