TASK$3[30$ pts$.]$: Figure depicted below shows the topology of a $4-$bit shift register when implemented structurally using D$-$Flip$-$Flops. Design a Verilog model to describe this functionality using a single procedural block and non$-$blocking assignments instead of instantiating D$-$Flip$-$ Flops. The figure also provides the block diagram for the module port definition. Use the type wire for the inputs and type reg for the outputs. Have your test bench change the input pattern every $40$ ns using delay within the procedural block and simulate your design to verify the functionality using Modelsim$.$