Task $3-6$: Create Additional Tests.

You will be using the brainless CPU as a subcircuit in Lab $4.$ Therefore, we want to make sure it

is working properly now rather than trying to debug it while working on Lab $4.$ In this task,

you$$ll create additional tests to verify that your circuit is$,$ in fact, working properly. Make three

copies of brainless$\_$stim.v and name them brainless$\_$ext$\_$write.v$,$ brainless$\_$int$\_$write.v$,$ and

Version $1\mathrm{.}1$ Fall $202418$

brainless$\_$alu.v$.$ Then, modify the inputs and expected outputs in each so that you perform the

following additional tests:

$1.$ Write a value from data$\_$in to an address in the program$\_$ram. This is an external write

to the RAM. $($brainless$\_$ext$\_$write.v$)$

$2.$ Store a nonzero value from the accumulator to an address in the program$\_$ram. This is

an internal write to the RAM. $($brainless$\_$int$\_$write.v$)$

$3.$ Demonstrate any two additional ALU functions, storing the results in the accumulator.

This may be done with a single simulation. The ALU functions may not be the pass

through or addition functions used in the example program provided in

brainless$\_$stim.v$.($brainless$\_$alu.v$)$

For each of the above, modify the stimulus and expected response as needed and run them

with iverilog. When they work as expected, paste the stimulus you used and a screenshot of the

waves similar to Figure $16$ into your template. For the stimulus, just paste in the values assigned

to test$\_$vals as shown in Figure $17.$

test$\_$vals$[0]=28\text{'}$h$0\_0\_0\_0\_0\_0\_4$; $//$ reset $-$ this should always be the first vector

test$\_$vals$[1]=28\text{'}$h$3\_3\_3\_0\_0\_3\_1$; $//$ get $3$ into the accumulator

test$\_$vals$[2]=28\text{'}$h$8\_5\_$D$\_0\_1\_5\_1$; $//$ add $3+5$ and store in the accumulator

test$\_$vals$[3]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$; $//$ do nothing the rest of the way

test$\_$vals$[4]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

test$\_$vals$[5]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

test$\_$vals$[6]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

test$\_$vals$[7]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

Figure $17.$ Example of what to paste in your template.

For the two tests which write to the RAM, make sure that the RAM value shows up on the

data$\_$bus output so it can be seen. Do this by properly controlling the select lines to the muxes.

To create these tests, use the same approach we took for the example test in brainless$\_$stim.v$.$

Ask yourself where the data is now and how the controls need to be set to get the data where

you want it$.$

Text file to be used here:

$`$timescale $1$ns$/1$ns

$//$ IMPORTANT: DO NOT MODIFY ANYTHING BETWEEN HERE AND $*****$

$//$ Module to provide stimulus to the brainless CPU

module brainless$\_$stim$($num$\_$tests,values,addr$)$;

output $[3$:$0]$ num$\_$tests; $//$ how many tests to apply

output $[27$:$0]$ values; $//$ the values to apply plus expected response

input $[2$:$0]$ addr; $//$ the address into the memory of values

reg $[27$:$0]$ test$\_$vals $[0$:$7]$; $//$ memory to hold the input and expected output

initial $//$ check for too many tests

begin

#$1$ if $($ num$\_$tests $>8)$

begin

$display$("$Too many tests $-$ the limit is $8!")$;

$finish;

end

end

assign values $=$ test$\_$vals$[$addr$]$;

$//$ The bits of the test$\_$vals memory are:

$//27$:$23-$ accum The expectd accumulator output

$//23$:$20-$ data$\_$bus The expected data$\_$bus value

$//19$:$16-$ alu$\_$out The expected alu output

$//15$:$12-$ data$\_$in The data$\_$in input

$//11$: $8-$ addr$\_$bus The address bus input

$//7-$ invert An ALU control input

$//6-$ arith An ALU control input

$//5-$ pass An ALU control input

$//4-$ load$\_$acc Load the accumulator

$//3-$ acc$\_$to$\_$db Select the accumulator value

$//2-$ reset Reset the circuit

$//1-$ write Write a value into the RAM

$//0-$ read Select the program$\_$ram value

$//$ IMPORTANT: ONLY MODIFY BELOW THIS LINE $*****$

assign num$\_$tests $=8$; $//$ how many tests you want to run

$//$ Each assignment to test$\_$vals$[$#$]$ is one test.

$//$ NOTE: The maximum number of tests is $8,$ and they are numbered $0-7.$

$//$ NOTE: The tests MUST be numbered consecutively starting with $0.$

$//$ NOTE: At least the first test should be reset!

$//$ For the bit assignments, see the comment $14$ lines above this line

initial

begin

test$\_$vals$[0]=28\text{'}$h$0\_0\_0\_0\_0\_0\_4$; $//$ reset $-$ this should always be the first vector

test$\_$vals$[1]=28\text{'}$h$3\_3\_3\_0\_0\_3\_1$; $//$ get $3$ into the accumulator

test$\_$vals$[2]=28\text{'}$h$8\_5\_$D$\_0\_1\_5\_1$; $//$ add $3+5$ and store in the accumulator

test$\_$vals$[3]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$; $//$ do nothing the rest of the way

test$\_$vals$[4]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

test$\_$vals$[5]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

test$\_$vals$[6]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

test$\_$vals$[7]=28\text{'}$h$8\_0\_0\_0\_0\_0\_0$;

end

endmodule