Task $4$: Analysis of Gate Delays and Flip$-$Flop Timing $[20$ Marks$]$

Consider the gate$-$level implementation of the circuits in Task $1$ and Task $2.$ Analyze the effect of gate delays and flip$-$flop timing on the system performance.

$-$ Assume the following gate delays: AND $(30$ ns$),$ OR $(20$ ns$),$ NOT $(10$ ns$).$

$-$ For the D flip$-$flop in Task $2,$ assume a setup time of $10$ ns and a hold time of $5$ ns $.$

$-$ Calculate and discuss the impact of these delays on the timing diagrams and overall circuit performance for both tasks.