TASKS:

1. In a single .v file, write modules for the following state elements (Using Verilog Code)

a. Gated RS-latch (Structural)

b. Negative edge-triggered JK Flip-Flop (Behavioral)

c. Negative edge-triggered D-Flip-Flop with asynchronous reset and synchronous enable (Behavioral)

d. A positive edge-triggered D-Flip-Flop implemented structurally in the Master-Slave pattern using D-latches (each D-latch, Behaviorally implemented).

2. Write a single testbench that goes through sufficient input patterns to showcase the behavioral differences of the above using the following paradigms (see testbench for sim3 for additional examples). Assume that the R and K inputs of elements a. and b. are the same, as are the J and S inputs. Similarly, assume that the D input is the same for c. and d. Create a module named Top that instantiates state elements a. through d. and tests them in parallel, driving their outputs to its outputs.

Testbench paradigms:

a. Clock generation via

reg clkSlow;

reg clkFast;

always #7 clkSlow = ~clkSlow;

always #2 clkFast = ~clkFast;

b. Use a behavioral unconditional modulo up-counter with reset to keep track of time:

reg [7:0] count;

always@(posedge clkFast)

begin

if (reset)

count <= 8h00;

else

count <= count +8h01;

end

c. Use clkSlow as the clock for all clocked/gated logic elements from task 1. Use the counter driven by clkFast and comparators to force events to happen at a specific time in the test case or directly connect bits of count to inputs