The 74HC138 is a 3-to-8 decoder with a logic diagram as shown below. (a) Write behavioral VHDL model for this circuit using a case statement. (b) Write dataflow VHDL model for this circuit using the corresponding logical equations (as in Figure 2-57). (c) Make a structural VHDL model for this circuit (as in Figure 2-58) using AND gates and inverters. A2 Y6 YS El Y2 E3 Y1