The architects for this system have determined that this computer will use a $256-$address $(8-$bit address$)$

control store and have defined two classes of microinstruction. Each class of microinstruction will decode

the microinstruction fields in a different way. This is advantageous as it decreases the number of bits

required for each microinstruction $($and therefore decreases the necessary size of the ROM$).$ The MSB of

the microinstruction will be used as a MODE bit to indicate the type of instruction and aid in the decoding.

The first class of microinstruction will be used to control the datapath by determining the control signals

outputs of the unit. In addition, one bit in this class of microinstruction $($MW: Memory Write$)$ will be used to

control the Write Enable output of the control unit.

The second class of microinstruction will be microsequencing$/$branch instructions used to perform the

explicit sequencing of the control unit. The sequencing microinstruction consists of two fields. The first is a

$3-$bit field CONDITION and the second is an $8-$bit field NEXT$\_$ADDRESS $($note that this is sufficient to

select any address in the control store$).$ If the condition specified by CONDITION is true then the

microinstruction at NEXT$\_$ADDRESS must be executed next $($CAR $$ NEXT$\_$ADDRESS$)$ otherwise the

next microinstruction is implicitly chosen $($CAR $$ CAR $+1)$