The cache for this problem has 16 words. You are going to evaluate the cache performance based on different mapping schemes, and different size blocks, to try to come up with the best mapping and block arrangement for this series of memory access calls.

Your mappings will be: 16 one-word blocks, Direct Mapping 16 one-word blocks, Fully Associative Mapping 4 4-word blocks, Direct Mapping 4 4-word blocks, Fully Associative Mapping 4-way Set-Associative, 16 one-word blocks

For each of the schemes, 1. Fill out the top table of tags 2. Show the placement of the block in the bottom table 3. Count the hits and misses 4. Compare the hit/miss ratios for the different mappings and block arrangements

If you were designing the cache, what do you think would have to most impact on the performance: larger block sizes, or different mapping schemes? Explain your reasoning.

Word Address	Word Bit Address	Direct 16 Tag	Direct 4 Tag	Fully Assoc. 16 Tag	Fully Assoc. 4
2	00000010	0000 m	0000m	00000010m	000000m
3	00000011	0000 m	0000 h	00000011 m	000000 h
11	00001011
16	00010000
21	00010101
13	00001101
64	01000000
48	00110000
19	00010011
11	00001011
3	00000011
22	00010110
4	00000100
27	00011011
6	00000110
11	00001011

# hits : # misses ______ _____ _________ _________ CAT size in bits: 16x5 = 80 4x5 = 20 with dirty bit: 16x6 = 96 4x6 = 24

16 Blocks	Direct Map 1word blocks	Associative 1word blocks	4 Blocks	Direct Map 4-word block	Associative 4-word block
0 (0000)		00000010	00	0000	000000
1 (0001)		00000011
2 (0010)	0000,
3 (0011)	0000
4 (0100)			01
5 (0101)
6 (0110)
7 (0111)
8 (1000)			10
9 (1001)
10 (1010)
11 (1011)
12 (1100)			11
13 (1101)
14 (1110)
15 (1111)

4-way Set Associative with 1-word blocks

Word Address	Word Bit Address	4 way set Tag
2
3
11
16
21
13
64
48
19
11
3
22
4
27
6
11

# hits : # misses _____________ CAT size in bits: ____________

4 way sets	Slot 1	Slot 2	Slot 3	Slot 4
0 (00)
1 (01)
2 (10)
3 (11)