The circuit below has two identical flip$-$flops which are clocked at $25$MHz$,$ and the

synchronising flip$-$flop is sampling an asynchronous $5$MHz $($data rate$)$ input.

Given that $=0\mathrm{.}31$ns$,$ To $=9\mathrm{.}6$ x $10-18$ s and t su $=1$ns for a D$-$type flip flop from a

typical $0\mathrm{.}25$m CMOS ASIC process.

$$ Calculate the resolution time and MTBF of the circuit.

$$ If the clock frequency in the circuit above is quadrupled, calculate the effect

on MTBF and comment on its change?

$$ Show how the circuit above can be modified to improve the MTBF$,$ by adding

an additional flip$-$flop. Give an expression to estimate the new MTBF$,$ and

calculate the new value.

D Q D QCombinational

logic

CLOCK

$6\mathrm{.}7$ ns

Synchroniser Flip$-$flop in

design

Asynchronous

input