The code is in the second picture

Q2: Draw the pipeline diagram for the code in Q1 for a 2-way multiple-issue 5-stages pipelined datanath I1: ORI $s,$,5 I2: ADDI $s1,$0,10 I3: ADD \$s1, \$se, \$s1 I4: LW $s,4($s1) I5: ADD $s,$s,$s I6: SW \$se, 4($s1) Q1: Consider the following MIPS assembly language code: Draw the pipeline diagram (complete the table below) showing the timing of the code instructions on the 5-5tage pipeline (IF, ID, EX, MEM, WB). The pipeline supports forwarding and pipeline stall. Draw an arrow showing forwarding between the stage that provides the data and the stage that receives the data. Show all stall cycles (draw an X in the box to represent a stall cycle). Determine the number of clock cycles to execute this code. I': ORI \$s., \$., = It: ADDI \$si, \$., 1. Ir: ADD \$51, \$s+, \$51 It: LW \$s., 7($s1) I2:ADD \$s*, \$s*, \$s. IV: SW \$S., t($s)