The Data Path

The data path is the machine that is really doing the entire data computation. The module head is given below to help you start. The right way to design the data path is: (1) based on the algorithm, design the block diagram which contains adders, comparators, registers, , and the connections; (2) identify the control signals (e.g., load_data, incr_delta, find_next_sq) whose activations enable the data path to compute; (3) identify flag signals (e.g., finish) to tell the controller what is happening in the data path.

module sqrt_data_path (num, load_data, incr_delta, find_next_sq, clk, finish, result

);

input load_data, incr_delta, find_next_sq, clk;

input [6:0] num;

output reg finish;

output [3:0] result;

We have 8 switches on the FPGA board, so we use 7 switches to input the square number (called num above). The one switch left is used to clear (reset) the registers. So, the largest square number that can be represented in this data representation is 121 and the sqrt is 11.

Control signal load_data is used to load the square number from switches to register Rdata. Control signal incr_delta is used to increment Rdelta by 2. Control signal find_next_sq is used to load the new square number (by adding Rdelta and Rn) into Rn. These three control signals are generated by the controller. Do we need to implement a clear signal to reset all registers in the data path? The answer is NO, because the registers will be initialized data in iteration 1.

Flag signal finish is use to tell the controller (from data path) that the computation is finished and the entire process must be stopped. Output result, which outputs the sqrt computed, will be presented to a bin2bcd module for the purpose of converting the binary result to bcd digits. The bcd digits finally will be displayed by seven-segment displays.