The full subtractor (also subtracter) is a device that accepts three inputs: 3, y, and b_in and 1. produces two outputs: b-out and d according to the truth table shown in Table1.2. Table 1.2: The truth table of a full subtractor. x y b_in b_out d 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 10 0 0 1 10 1 0 0 11 0 0 0 1 1 1 1 1 2. (Structural Style) (a) Write a Verilog HDL module to describe the full subtractor obtained from from table 1.2 in structural style using instantiations of gate primitives. (b) Write a test bench and verify if the module behaves as a full subtractor