The gates have below $($rise$,$ fall$)$ delay numbers.

Let $A=B=C=1$ until time $t=0.$ At $t=0$ all inputs flip and remain in that state.

$\backslash$table$[[,$Rise delay$($ns$),$Fall delay$($ns$)],[$NOT$,15,20],[$AND$,10,15],[$BUFFER$,10,20],[$XOR$,25,20]]$

For $t>0$ output $Z=0$ for a duration of $\_\_\_$ ns$.$