the Instruction Set Architecture document:

1. The function F is defined as F(1) = F(2) = F(3) = 1 and for n 3, F(n + 1) = F(n) + (F(n-1). F(n - 2)) i.e., the (n + 1)th value is given by the sum of the nth value and the multiplication of the (n-1)th and (n-2)th values. (a) Write an assembly program for computing the kth value F(k), where k is an integer bigger than 3 read from a memory location M, and storing F(k) at memory location M. Use the instruction set in the Instruction Set Architecture document: (b) Consider a pipelined processor, where the pipeline stages are F (fetch), D (decode), R (register read), E (execute) and W (write back). Describe what happens in the pipeline stages for the var- ious types (data movement, data processing, control) of instruc- tions. (10 marks] (c) Show the execution of your program on the above pipelined pro- cessor for k = 5 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with a capacity of 12 instructions, and that there is no resource conflict between fetching instructions and executing data transfer instructions. Explain where and why delay slots appear. Instruction Set Architecture We present a list of instructions typical machine. In data-movement and control instru direct (memory) M, indirect memory) [M]. res Data processing instructions use immedia counter and a