The memory is byte addressable Memory accesses are to 1-byte words (not to 4-byte words). Virtual addresses are 12 bits wide Physical addresses are 12 bits wide. 0 . The page size is 256pytes The TLB is 4-way associative tib (E-4) with 1 sets (S 1) and a total of 4 entries The TLB and a portion of the page table contents are as shown below TLB Page Table 0x1 0x9Y 0x9 Oxe Y |Set # Way #3110x2|0x4 | Yl0xaloalY Wa y#0 Way #1 Way #2 0: 0x7 0x8 Y Oxf 0x6Y Assume that memory address Oxd76 has been referenced by a load instruction. Determine the virtual page number (VPN) and use that to compute the TLB index and tag that would be used to check the TLB for the translation entry Indicate if the entry is in the TLB (Y/N) Indicate if the memory reference has a valid entry in the page table whether it hits in the TLB or not. n toble to tranelate the VDl to a nhueical nane number (PPN).and then the