The MemoryMap pdf from UR Courses shows memory as a table of $32$ bit words with the address

of each word repeatedly ending in $0$x$0,0$x$4,0$x$8,$ and $0$xC$.$ What do we know about the LSB of each

of these addresses $($the address, not the value stored at the address which could be anything$)?$ Do we

know the second LSB$?$ Figure $4\mathrm{.}26$ states the LSB of exception vectors should be set to $1$ to indicate

Thumb state. Figure $4\mathrm{.}3\mathrm{.}1$ shows an example with the reset vector containing address $0$x$101,$ however

the actual address pointed to is $0$x$100.$ For Cortex$-$M processors would we ever see an ISR start at an

address with the LSB equal to $1?$