The next VHDL concurrent statements represent a tri-state bus system that controls one source passage to...

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The next VHDL concurrent statements represent a tri-state bus system that controls one source passage to the Bus. What is the right condition that makes the next statements work correctly? Bus <= A when EnA = '1' else "ZZZZ"; Bus<= B when EnB = = '1' else "ZZZZ" Bus <= C when EnC = '1' else "ZZZZ"; Bus <= D when End = '1' else "ZZZZz"; 1. Only one Enable EN should be '1' and others should be '0' O2. Anyone source that its Enable = '0' will pass even if more than one EN is '0' for the others. 3. Anyone source that its Enable = '1' will pass even if more than one EN is '1' for the others. O4. The circuit is entirely wrong and will not allow any signal to pass. O 5. Only one Enable EN should be '0' and others should be '1' The next VHDL concurrent statements represent a tri-state bus system that controls one source passage to the Bus. What is the right condition that makes the next statements work correctly? Bus <= A when EnA = '1' else "ZZZZ"; Bus<= B when EnB = = '1' else "ZZZZ" Bus <= C when EnC = '1' else "ZZZZ"; Bus <= D when End = '1' else "ZZZZz"; 1. Only one Enable EN should be '1' and others should be '0' O2. Anyone source that its Enable = '0' will pass even if more than one EN is '0' for the others. 3. Anyone source that its Enable = '1' will pass even if more than one EN is '1' for the others. O4. The circuit is entirely wrong and will not allow any signal to pass. O 5. Only one Enable EN should be '0' and others should be '1'

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