The organization of a cache for a byte-addressable memory is shown in the figure below. The cache holds 4K of data (not including the overhead). Each block contains one word. Answer the following questions (write unknown if the answer cannot be discerned from the information provided).

Is it a direct mapped cache or set-associative cache?

What is the number of lines (sets) in cache?

Is the cache write-through or write-back?

What is the number of index bits in the address?

What is the number of tag bits in the address?

What is the total size of the cache, including the overhead?

For the purpose of this question only assume that the size of the index field in the address is 2 bits. Assuming that the cache is initially empty, label each the list as a hit or a miss and show the final contents of the cache. 0ff00f70, 0ff00f60, 00ff0fa0, 0fe0012c, 0ff001e8, 00f00f64, 0f000144, 0ff00000, 0ee01016, 0ff00014, 0fe00204, 0ff00f74, 0ff00f28, 0ff00000

o Byte offset 31 30 Index ndex V Tag Data VTag Data V Tag Dat VTag Data 4x1 select Hit