The pipelined RISC$-$V processor $($with hazard unit$)$ is running the following code snippet:

add s$1,$ zero, to

Iw t$4,25($t$0)$

add s$3,$ s$3,$ s$1$

or s$4,$ s$1,$ s$2$

Stages' Shortcut:

F: Fetch

D: Decode

E: Execute

M: Memory

W: Write Back

NA: No Action $($nothing is being done at this stage$)$

Fill the table with the correct stage in every cycle:

$\backslash$table$[[$Instruction$,\backslash$table$[[$Cycle$],[1]],$Cycle $2,$Cycle,,Cycle,,,,Cycle,,Cycle,,Cycle $8],[\backslash$table$[[$add s$1,$ zero,$],[$to$]],\backslash$table$[[$F$]],$D$,$E$,,$M$,,$W$,,$NA$,,$NA$,,],[$Iw t$4,25($t$0),$NA$,F,$D$,$hat$(v),$E$,$hat$(v),M,$hat$(v),$W$,$hat$(v),$NA$,$~~$,],[\backslash$table$[[\backslash$table$[[$add s$3,$ s$3,],[$s$1]]]],$NA$,$NA$,$F$,$hat$(),$D$,$hat$(v),$E$,$hat$(v),$M$,$hat$(),$W$,$~~$,$NA hat$(v)$