The RISC-V data path design discussed in the Textbook considered only a subset of that processor instructions. In this project, you are required to augment the design of the data path for the following instructions:

• Add immediate: Addi Xd, Xs, imm
• Load Sum: Lws rd, rs1, rs2; where Reg[rd]=Mem[rs1+rs2].

For example, if x5=20, x6=30 then the instruction Lw1 x4,x5,x6 will load X4 with the contents of memory location 50.

• Swap rs1, rs2 swaps contents of the two registers.
• Store Sum: SS rs1, rs2, imm; Mem[rs1]=rs2+imm

1. Problem Statement
2. Design Details

For each instruction from the above list:

1. Define the most appropriate instruction format for the instruction.
2. Define the new functional units (if any) that is needed for this instruction.
3. Define the modifications ( if any) that has to be done to existing data path. If not, justify that the current data path is sufficient.
4. Define any new control signals (if any) to be provided by the control unit.
5. Define the settings of all control signal for that instruction.
6. Draw the data path that demonstrates the implementation of that instruction.

3. Complete data path: Draw the complete data path units along with the control signals for all the instructions. ( Those implemented in class and the above listed instructions)
4. Performance: Discuss how the performance of the processor is affected by the new instructions.