The SystemVerilog statement that performs the bit$-$wise AND of the $16$ least significant bits of data with $0$xC$820.$ It then ORs these $16$ bits to produce the $1-$bit result.

Group of answer choices

result $=|($data$[15$:$0]$ & $16\text{'}$hC$820)$;

result $=|($data$[15$:$0]|16\text{'}$hC$820)$;

result $=$ & $($data$[15$:$0]$ & $16\text{'}$hC$820)$;

result $=($data$[15$:$0]$ & $16\text{'}$hC$820)$;