The task is to design a structural comparator for signed and unsigned number and then to write a complete code for verification. You should search for information about the needed logic$/$circuits to implement a comparator for signed and unsigned numbers.

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The Task:

Your task is to structurally create a comparator for signed numbers $(2$s complement representation$)$ and unsigned numbers. The circuit will have the following main inputs and outputs

$1-$ First number A: $6$ bits

$2-$ Second number B: $6$ bits

$3-$ Selection S: $1$ bit to select how to consider the numbers $($signed or unsigned$)$ and thus how comparator will work

$4-$ First output $$Equal$$ : will produce $1$ if A$=$B$.$

$5-$ Second output $$Greater$$: will produce $1$ if A$>$B$.$

$6-$ Third output $$Smaller$$: will produce $1$ if A$<$ B$.$

The Comparator is to be built structurally from a library of gates, which contains the following devices:

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Gate$\backslash$ID

Delay ns

INV

$2$

NAND

$7$

NOR

$7$

$$AND

$8$

OR

$8$

XNOR

$9$

XOR

$10$

Your UDP $($Max inputs $=4)$

$12$

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$$ All combinational parts of your design should be built structurally from these basic gates and the defined delays $($consider that the delay will not change even if the gate has more than $2$ inputs$).$

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After that registers should be added to the inputs$/$outputs of the circuit to make the circuit synchronous $($thus$,$ we need to add more inputs such as clk$).$

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You should determine the maximum latency of the comparator. And therefore, what is the maximum frequency of the clock that can be applied to the registers. You should verify that your system is working for all possible values of the inputs. Also, you should introduce an error in your design and to do a verification that will discover the error and write it to the console screen.