There is a Ring Counter whose code is below.

Obtain

a$)$ Do analysis of the flip flop to be used where the preparation time is determined in Verilog

$$

b$)$ tweak the code so that timings are implemented correctly to avoid metastability

$$

Use the following flip flop code provided

module FFD$\_$PC$($Q$,$NQ$,$D$,$CLK$,$PR$,$CLR$)$;

$$

input D$,$CLK$,$PR$,$CLR;

output Q$,$NQ;

wire wRm$,$ wSm$,$ Qm$,$ NQm$,$ wRe, wSe, nCLK$,$ nD$,$ nPR$,$ nCLR;

$$

not

$$ not$1($nCLK$,$ CLK$),$

$$ not$2($nD$,$D$),$

$$ not$3($nPR$,$PR$),$

$$ not$4($nCLR$,$CLR$)$;

$$

and

$$ and$1($wRm$,$D$,$nCLR$,$nCLK$),$

$$ and$2($wSm$,$nD$,$nPR$,$nCLK$),$

$$ and$3($wRe$,$Qm$,$CLK$),$

$$ and$4($wSe$,$NQm$,$CLK$)$;

$$

nor

$$ nor$1($Qm$,$NQm$,$wRm$,$PR$),$

$$ nor$2($NQm$,$Qm$,$wSm$,$CLR$),$

$$ nor$3($Q$,$NQ$,$wRe,CLR$),$

$$ nor$4($NQ$,$Q$,$wSe,PR$)$;

$$

endmodule

Use the following clock.v module to generate the flip flop clock signal

module reloj$($clk$)$;

$$

output clk;

$$

reg clk;

$$

initial

$$ #$1$ clk$=0$;

$$

always

$$ #$5$ clk$=$~clk;

$$

endmodule