These are verilog codes that simulate direct FIR filter and transpose FIR filter. When I simulated using the following code, TRAN$\_$out and DIRE$\_$out are pushed out by $80$ns compared to out$\_$mat as shown in the attached picture, resulting in an error.$($clock cycle$=10$ns$)$ I tried using the delay using # properly outside and inside the door for, but I couldn't find the answer. Please let me know which part of the code should be modified.

$`$timescale $1$ns$/10$ps

module sti$\_$FIR$\_$filter;

reg clk$,$ reset;

reg $[25$:$0]$ sig$\_$mat $[0$:$255]$;

reg $[25$:$0]$ out$\_$mat;

reg $[25$:$0]$ TRAN$\_$out;

reg $[25$:$0]$ DIRE$\_$out;

wire $[13$:$0]$ c$0=14\text{'}$h$3$aa$4$ ;

wire $[13$:$0]$ c$1=14\text{'}$h$1433$;

wire $[13$:$0]$ c$2=14\text{'}$he$37$;

wire $[13$:$0]$ c$3=14\text{'}$h$1$a$57$;

wire $[13$:$0]$ c$4=14\text{'}$h$917$;

wire $[13$:$0]$ c$5=14\text{'}$h$2$c$1$d;

top$\_$FIR$\_$filter FIR$($clk$,$ reset, c$0,$ c$1,$ c$2,$ c$3,$ c$4,$ c$5)$;

integer err$=0$;

initial

begin

clk $=1$;

reset $=0$;

#$10$

reset $=1$;

end

always #$5$ clk $=$ ~clk;

initial $readmemh$("$input$\_$vector$\_$hex.txt$",$ FIR.DIRECT$\_$INPUT$\_$MEM.array$)$; $//$check the path of memory rocation $($module instance$)$

initial $readmemh$("$input$\_$vector$\_$hex.txt$",$ FIR.TRANS$\_$INPUT$\_$MEM.array$)$; $//$check the path of memory rocation $($module instance$)$

integer i$=0$;

initial

begin

$readmemh$("$output$\_$vector$\_$hex.txt$",$ sig$\_$mat$)$;

begin

#$(110)$;

for $($i$=0$; i$<mn>2</mn><mn>5</mn><mn>6</mn>$; i$=$i$+1)$

begin

out$\_$mat sig$\_$mat$[$i$]$;

TRAN$\_$out FIR.DIRECT$\_$OUTPUT$\_$MEM.array$[$i$]$;

DIRE$\_$out FIR.TRANS$\_$OUTPUT$\_$MEM.array$[$i$]$;

if$(($TRAN$\_$out $!=$ out$\_$mat$)||($DIRE$\_$out $!=$ out$\_$mat$))$ err $=$ err $+1$;

#$(10)$;

end

$stop;

end

end

endmodule