This assignment is about modifying a verilog implementation of the multi-cycle design.

// Universal constants 'define RUNTIME 500 // How long simulator can run 'define MEMDEL 25 // MEMory read delay 'define CLKDEL 5 // CLock delay 'define WORD [31:0] // size of a data word 'define REG [4:0]// size of a register number 'define STATENO [7:0] // size of a state number 'define MEMDIM [1023:0] // number of memory location to implement // Control signals "define ALUadd ALUMUX = (Y + BUS); 'define ALUand ALUMUX = (Y \& BUS); 'define ALUxor ALUMUX =(Y BUS): "define AlUor ALUMUX = (Y | BUS): 'define ALUsll ALUMUX = (BUS Y); "define ALUslt ALUMUX = ( Y