1. This code is for designing a FSM in Mealy machine. There are four errors. Find and correct them.

This code is Verilog

module edgeDetector

(

input wire clk, reset,

input wire level,

output reg Mealy_tick);

localparam

zeroMealy = 1'b0,

oneMealy = 1'b1;

reg stateMealy_reg, stateMealy_next;

always @(posedge clk, posedge reset)

begin

if(!reset)

stateMealy_reg <= zeroMealy;

else

stateMealy_reg <= stateMealy_next;

end

end

always @(stateMealy_reg)

begin

stateMealy_next = stateMealy_reg;

Mealy_tick = 1'b1;

case(stateMealy_reg)

zeroMealy:

if(level)

begin

stateMealy_next = oneMealy;

Mealy_tick = 1'b1;

end

oneMealy:

if(level)

stateMealy_next = zeroMealy;

endcase

end

endmodule