This exercise refers to the files:

XOR$2$gate.sv

XOR$2$gate

testbench.sv

a$.$ After loading these fies into the EDA playground, run a simulation and include a timing diagram of your simulation in your report.

b$.$ Edit the design file and convert the Verilog code to a behavioral model that performs the same function as the structural model. After doing this, run a simulation and include your code and a timing diagram of your simulation in your report.