This homework will make use of the MIPS assembly language, for which we are designing a small processor. The datapath of our small processor is given below:

And we are supporting only the following instructions:

and, or$,$ add, sub, slt$,$ lw$,$ sw$,$ beq

$3.$ Assume that the components have the following latencies:

$\backslash$table$[[$Unit I$-$Mem,Add Mux,ALU,Regs,D$-$Mem,Control,$],[$Latency $400$ps$,100$ps$,30$ps$,120$ps$,200$ps$,350$ps$,100$ps$]]$

Note that several paths through the processor are going to be active while it fetches and executes a single instruction. Even in this simple processor.

The data path is active $($of course$)$; but there is also a path that is updating the PC$,$ and a path through PC$,$ A$,$ and G$,$ setting the control bits.

Compute the latency of each of these paths for the case of an Iw instruction. If this were the slowest operation, what is the max rate in $Hz$ we could clock this processor?

$[3$ points$]$