Question: This is in Structual Verilog code: The circuit accepts two 2-bit inputs player_a[1:0] and player_b[1:0] and provides three outputs player_a_wins, player_b_wins, and tie_game. The circuit

This is in Structual Verilog code:

The circuit accepts two 2-bit inputs player_a[1:0] and player_b[1:0] and provides three outputs player_a_wins, player_b_wins, and tie_game. The circuit should be designed as a judge for the game Rock, Paper, Scissors. Remember that in this game, rock beats scissors, scissors beats paper, and paper beats rock. If both players make the same move, the game is tied.

Each of a players possible moves should correspond to a two-bit value, as follows:

Players Move	Rock	Paper	Scissors
Input Value	11	10	00

The value of the outputs player_a_wins and player_b_wins should equal one if the associated player wins, and should equal 0 otherwise. The output tie_game should equal 1 if the players tie, and should equal 0 otherwise. The outputs are mutually exclusive only one of the three outputs can equal one for any combination of valid input values, and one of the three will equal one for every valid input combination. For example:

If player_a = 11 and player_b = 00, then player_a_wins = 1, player_b_wins = 0, and tie_game = 0, since rock crushes scissors.

If player_a = 11 and player_b = 10, then player_a_wins = 0, player_b_wins = 1, and tie_game = 0, since paper covers rock.

If player_a = 00 and player_b = 00, then player_a_wins = 0, player_b_wins = 0, and tie_game = 1, since both players played scissors.

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