This is the question from Lab4, CSC258 Winter 2016, UTSG. Computer Organization

I am trying to design a 8-bit counter in verilog(using a strange t-flipflop) and I am asked "Your code should use a module that is instantiated eight times to create the counter".

So I think it should be something like this:

always@(posedge clock, posedge reset) begin

(repeat 8 times) tFlipFlop(.T(inputT), .in(element_stored_last_time), .out(new_element));

end

Clearly, I cannot use module in always block. But if I put tFlipFlop outside the always block(with loop), how to do it?

Maybe my idea is not correct. Is there a better idea?

In this function ,my input value and output value are the same, as I just want to change the value stored in the register. Can i input and output a same value?

PLEASE DO NOT give me a function like this:

reg [7:0]out;

assign out = 2'b00000000;

always@(posedge clock, posedge reset) out = out +1;

I DON'T think it instantiates t flip-flop 8 times or you can persuade me and the tutor who will check my prelab.

Thank you very much!