This lab is going to model some functionality that might be employed in a simple game that is intended to test a persons reactions. It will involve two counters that will move in opposite directions; one will count up, the other will count down. We will need to imagine that the numbers are displayed to the person playing the game.If we had a physical implementation of this game, the player would have a button to control the counters. When the button is pressed, the two counters begin to count. And they continue to count as long as the button remains depressed. When the button is released, the counters stop counting. The objective of the game is to try to stop when both counters show the same value.Were going to use 3-bit counters as the primary building block for this design. A 3-bit counter can express 8 possible values (from 0 to 7), which is an even number of values. If we have an up counter and a down counter running thru an even number of values, and running on the same clock, they will always match at a given value every time they run thru their sequence. So we are going to modify the behavior of these counters so theyonly range thru an odd number of values, specifically they will stay within the range of 1 to 5.Unfortunately, in our remote environment, we dont have a button to use control the counting. But we will model this withan input to our design that we will call Stop. Stop will be the inverse of the button being pressed, i.e., when Stop is not asserted, the counters will count, and when Stop is asserted the counters will stop counting and a result will be generated.To indicate the results of the game, there will be two output signals:A win signal is asserted if the two counter valuesmatchwhen Stop is asserted.A lose signal is asserted if the two counter valuesdo not matchwhen Stop is asserted.While Stop is not asserted, and the counters are counting, neither the win nor the lose signal is asserted.You might envision that this design could support multiple speeds. As the speed increases, the game becomes more challenging. But since well be doing this in simulation, we will not be concerned withthe actual speed at which the circuit is running. You will be given a Counter module, which is represented by the two blocks in the middle of the diagram above. These counters will be standard 3-bit counters, i.e., they will be designed to count the entire range of 0 to 7. But note that this Counter module has a number of inputs (besides Clock and Reset):CntEn which will enable the Count value to change on the next rising edge of the clockDir which will determine the direction in which the counter will count. If Dir=1 the counter will count up. If Dir=0 the counter will count down. Note in the diagram that were going to be explicitly forcing one of the counters to be an up counter and one to be a down counter. Load when asserted, this will cause the Count output to change (at the next rising edge of the clock) to the 3-bit value on the New inputNew a 3-bit value that will be loaded into the counter (on the next rising edge of the clock) if and only if the New signal is assertedYou will be designing the other three modules (Up Control, Down Control, and the WinLose module) and connecting everything up in a top level module.The behavior of these modules are described below. You will be writing the Verilog for each of these as your pre-lab submission.

THE FOLLOWING TWO, please help:

1.UpControlThis module takes a 3-bit count value as input, andgenerates a Load signal and 3-bit new count value as outputs. Since were aiming for a counter that counts from 1 to 5, this module needs to assert Load when it sees the count input is the value 5, and it needs to cause the counter to load the value 1.2.DownControlThe inputs and outputs for this module are the same as UpControl, but in this case we need a module that will assert Load when it sees its count input shows the value 1, and it needs to cause the down counter to load the value 5.