This needs to be done

using logic works

Goal:

The purpose of this project is to demonstrate the use of Boolean logic and build basic circuits. Note that this lab assignment is group assignment with each group having either $2$ students or $3$ students.

Problem Statement:

The predominant storage inside computer systems are on disks drives. SCSI disks are the standard disks in most Unix Workstations from Sun, HP$,$ SGI, and other vendors. They are also the standard disks in Macintoshes and Higher$-$end Intel PC$\text{'}$s$,$ especially network servers. Consider the Wide Ultra$4$ SCSI which transfers data packets in $16-$bit bursts at $160$ MHz with a maximum throughput of $\backslash (320\backslash$mathrm$\{$MB$\}/\backslash$mathrm$\{$sec$\}\backslash ).$ The data transfers at higher rates can result in random$-$noise pulse changes from a $0$ to $1$ and $1$ to a $0.$ As the speed of processors and electronic communications increases, these parity flips become more prevalent and the inability to detect when these errors occur can be fatal. As a Design Engineer you have been requested to create system for the transmission of these $8-$bit packets from an I$/$O Controller to Memory using Error Correcting Code over $12-$bit data bus line. Wide SCSI contains a $68$bit bus; however for the sake of simplification we are only concerned with the data bits. The other bits in the SCSI bus are for bus arbitration, synchronization, power management, etc. In this project, we will use even parity.

Transmission Vectored Bit: A $4-$Bit Parity Vector $(\backslash (\backslash$mathrm$\{$P$\}\_\{1\}-\backslash$mathrm$\{$P$\}\_\{4\}\backslash ))$ are interlaced with the $8-$bit Data Vector $\backslash (\backslash$left$(\backslash$mathrm$\{$D$\}\_\{1\}$: $\backslash$mathrm$\{$D$\}\_\{8\}\backslash$right$)\backslash )$ :

$\backslash [$

$\backslash$mathbf$\{$P$\}\_\{1\}\backslash$mathbf$\{$P$\}\_\{2\}\backslash$mathrm$\{$D$\}\_\{1\}\backslash$mathbf$\{$P$\}\_\{3\}\backslash$mathrm$\{$D$\}\_\{2\}\backslash$mathrm$\{$D$\}\_\{3\}\backslash$mathrm$\{$D$\}\_\{4\}\backslash$mathbf$\{$P$\}\_\{4\}\backslash$mathrm$\{$D$\}\_\{5\}\backslash$mathrm$\{$D$\}\_\{6\}\backslash$mathrm$\{$D$\}\_\{7\}\backslash$mathrm$\{$D$\}\_\{8\}$

$\backslash ]$

$1)$ Create an ECC Generator, at the I$/$O Controller from the $8-$bit Data Vector. The output of the ECC Generator will be the $4-$Bit Parity Vector.

$2)$ Construct a $12-$bit Data Transmission bus to send the binary data and parity bits over to Memory.

$3)$ Construct an ECC Detector at Main Memory that corrects for single bit errors. Generally, an interrupt$/$error handler is used to handle errors from the OS$,$ for this exercise we will use $3$ Hex displays, $2$ for data and $1$ for an error status, for diagnostic purposes:

In the event that no error has occurred, your design must display the data transferred using the $2$ Hex data displays and a $"0"$ as an error status.

For single bit transmission errors, your system must correct the error and display the data along with $"$ C $"$ in the $3$rd Hex Display.

For multiple bit transmission errors, your design must display $"$E$"$ in the error status display.