This presentation segment is booked for $50$ minutes at the beginning of the day.

Your actual content can be $20-25$ minutes in length, the rest of the time will be

used in Q&A$.$ Your presentation topic is provided below, please do let us $($CC$\text{'}$d to

this email$)$ know if you have any questions or if you need any clarifications once you

review the topic.

Consider the following about System$-$on$-$Chip you need to emulate:

$1$

One Billion Gate Chip

Massive amount of SRAM memories

Handful of $($not shown$)$ PLLs to generate internal clocks

JTAG

DDR memories

Ethernet $($Packets in and out$)$

PCle $($configured as Root$-$Complex or End$-$point$)$

Flash Memories $($NAND$,$ NOR, $...)28-$Core

Deliverable

Presentation Slide

Please prepare a PowerPoint presentation on how to verify a custom embedded

processor combined with custom logic to implement a network switch with the use

of high level emulation environment $($SystemVerilog or UVM or C$/$C$++$ or SystemC

based$)$ running on Palladium or Veloce that can be used to verify at a sub$-$system

level and full system.

When in doubt, make an assumption, and discuss it in your presentation.

The presentation should address the following:

Minimize the time$-$to$-$bring up the platform, emulation capacity, test development

strategies, choose the

best emulation strategy $($ICE$,$ Virtual, TB acceleration$).$

Emulation performance optimization

Scalable environment architecture

Automated checking $/$ scoreboarding

Support for $($constrained random$)$ stimulus generation

Custom tranxactor developmentis booked for $50$ minutes at the beginning of the day.

Your actual content can be $20-25$ minutes in length, the rest of the time will be

used in Q&A$.$ Your presentation topic is provided below, please do let us $($CC$\text{'}$d to

this email$)$ know if you have any questions or if you need any clarifications once you

review the topic.

Consider the following about System$-$on$-$Chip you need to emulate:

'One Billion Gate Chip

Massive amount of SRAM memories

Handful of $($not shown$)$ PLLs to generate internal clocks

JTAG

DDR memories

Ethernet $($Packets in and out$)$

PCle $($configured as Root$-$Complex or End$-$point$)$

Flash Memories $($NAND$,$ NOR, $...)28-$Core

Deliverable

Presentation Slide

Please prepare a PowerPoint presentation on how to verify a custom embedded

processor combined with custom logic to implement a network switch with the use

of high level emulation environment $($SystemVerilog or UVM or C$/$C$++$ or SystemC

based$)$ running on Palladium or Veloce that can be used to verify at a sub$-$system

level and full system.

When in doubt, make an assumption, and discuss it in your presentation.

The presentation should address the following:

Minimize the time$-$to$-$bring up the platform, emulation capacity, test development

strategies, choose the

best emulation strategy $($ICE$,$ Virtual, TB acceleration$).$

Emulation performance optimization

Scalable environment architecture

Automated cscoreboarding

Support for $($constrained random$)$ stimulus generation

Custom tranxactor development