TITLE OF PROJECT : CLINIC QUEUE SYSTEM Do the verilog code and show waveform only

Project Design 2.1 Projects that can be implemented using digital circuits onto an FPGA chip, using Intel Quartus platform 2.2 Using hierarchical design approach. Design of the Functional Blocks in the hierarchy should be delegated among group members. 2.3 Your design stage should be including stage diagram, state table, ASM chart, etc. 2.4 Designs must be implemented and verified using the Intel Quartus software. 2.5 The output of the project must be demonstrated by using waveform