TO BE COMPLETED IN MODELSIM

Use the truth table to find the Sum of Minterms expression.

Reduce the expression using Boolean algebra.

Note in steps $3$ and $4$ in ModelSim choose File $>$ New $>$ Source $>$ Verilog from the menu to create

your HDL model and Test Bench. Then save your files to a directory of your choice, default

recommended. Next create a new project. You will need to copy the files to your project

directory, just as you did the in the ModelSim tutorial.

Create a Verilog Gate Level HDL model from your reduced expression. DO NOT USE

ASSIGN STATEMENTS FOR THIS HOMEWORK.

Create a test bench for all possible inputs for your model.

Using ModelSim simulate your model and create a timing $($Wave$)$ diagram and List, verify

your model is functioning correctly.