Translate this design directly to system Verilog code: 2 3514 14 3 bpb 360ot 3 Look up 1 N 3 digit next digit D S6 eu 95000 rext_n ok bounce cloch clock in clockso same design I 2 digit_next 3 digit a..g D reset_n w1 3 7 en[O).en(3) 4 clock clock_in clock50 D debounce It has two pushbutton switch inputs (reset_n and clock_in), a 50 MHz clock input (clock50), seven active-low segment outputs, (a through g), and four active-high digit-enables (en[3] through en[0]). To Value Out Assignment Name Location Location Location Location Location Location Location d dp e UUUUUUUUUUUU Location en[3] en[2] en(1 en[0] PIN_33 PIN_44 PIN_38 PIN_34 PIN_36 PIN_30 PIN_35 PIN_50 PIN_48 PIN_42 PIN_52 PIN_40 PIN_99 PIN_97 On reset_n clock_in clock_in reset_n clock50 Location Location Location Location Location Location Weak Pull-Up Resistor Weak Pull-Up Resistor Location On PIN_12 top side of display E LD5643B 12 en (3) 9 en[2] 8 en[1] 11 a 10f /b part number Translate this design directly to system Verilog code: 2 3514 14 3 bpb 360ot 3 Look up 1 N 3 digit next digit D S6 eu 95000 rext_n ok bounce cloch clock in clockso same design I 2 digit_next 3 digit a..g D reset_n w1 3 7 en[O).en(3) 4 clock clock_in clock50 D debounce It has two pushbutton switch inputs (reset_n and clock_in), a 50 MHz clock input (clock50), seven active-low segment outputs, (a through g), and four active-high digit-enables (en[3] through en[0]). To Value Out Assignment Name Location Location Location Location Location Location Location d dp e UUUUUUUUUUUU Location en[3] en[2] en(1 en[0] PIN_33 PIN_44 PIN_38 PIN_34 PIN_36 PIN_30 PIN_35 PIN_50 PIN_48 PIN_42 PIN_52 PIN_40 PIN_99 PIN_97 On reset_n clock_in clock_in reset_n clock50 Location Location Location Location Location Location Weak Pull-Up Resistor Weak Pull-Up Resistor Location On PIN_12 top side of display E LD5643B 12 en (3) 9 en[2] 8 en[1] 11 a 10f /b part number