Two improvements are considered to a base machine with a load/store ISA and in which floating-point arithmetic instructions are implemented by software handlers. The first improvement is to add hardware floating-point arithmetic units to speed up floating-point arithmetic instructions. It is estimated that the time taken by each floating-point instruction can be reduced by a factor of 410 with the new hardware. The second improvement is to add more first-level data cache to speed up the execution of loads and stores. It is estimated that, with the same amount of additional on-chip cache real-estate as for the floating-point units, loads and stores can be speeded up by a factor of 2 over the base machine.

Let F_fp and F_ls be the fraction of execution time spent in floating-point and load/store instructions respectively. The executions of these two sets of instructions are non-overlapping in time.

a) Using Amdahls speedup, what should the relation be between the fractions F_fp and F_ls such that the addition of the floating-point unit is better than the addition of cache space?

b) What are fractions F_fp and F_ls such that a speedup of 50% (or 1.5) is achieved for each improvement deployed separately?