uestion 2 Consider the Assemble program below. It is used to copy 3 byte-size data from program memory to data memory .cseg .org 0 rjmp start const:.db 0x12, 0x34, 0x56 start: I2 3 4 ldi ZL, low (const1) ldi ZH, high (const1) ldi YL, low (var) ldi YH, high (var) ldi r16, 0 loop: 1pm r17, Z+ st Y+, r17 inc r16 cpi r16, 3 brlo loop 6 9 done: rjmp done .dseg .org 0x200 var: .byte3 As we know, AVR architecture adopts a very simple pipleline mechanism with a "fetch-execution" cycle for each instruction. Each fetch operation takes 1 CPU cycle, but the number of CPU cycles for execution operations varies. In this program, LPM instruction take 3 CPU cycles to execute, ST takes 2, other in structions take 1 Answer the following questions by constructions the pipeline diagram for this program (only considering instructions lo to /o unless 111 is needed to be pre- fetched) (1) How many CPU cycles are needed to execute this program til jump into the dead loop, same to other questions)? [6 (2) Find out all structural hazards and control hazards during the execution of this program. [4 3) How many CPU cycles are needed to execute this program if a branch pre- (4) Calculate the improvement ratio (-(N-N')/N where N is the number of cycles without prediction and N" is the number of cycles with prediction) for the strategy in (4). [4]