URGENT PLS!!!!

Ql. Consider a combinational logic circuit as shown in Figure 1. Initial state for all lines is unknown (x). Single stuck-at fault analysis is assumed. AX D B C m out n 8 D X Figure 1 a) Find a test vector that can expose stuck-at-o at line h. [5 marks] b) Based on your answer in part (a), determine the singular cover and the D-cubes that are used to expose the stuck-at-0 at line h. [5 marks] c) Based on your answer in part (b), show the actions, operations and D-frontier to expose the fault. [10 marks) Q2. Referring to Figure 2, find a sequence of test vectors that can expose line c stuck-at 0 and d stuck-at 0 with the minimum number of clock cycles using time-frame expansion model (one sequence of test vectors, but can expose both faults). Initial state for all lines is unknown (x). Show the time-frame expansion circuit and the analysis. [20 marks) A A D Q C d B D o CLK Ql. Consider a combinational logic circuit as shown in Figure 1. Initial state for all lines is unknown (x). Single stuck-at fault analysis is assumed. AX D B C m out n 8 D X Figure 1 a) Find a test vector that can expose stuck-at-o at line h. [5 marks] b) Based on your answer in part (a), determine the singular cover and the D-cubes that are used to expose the stuck-at-0 at line h. [5 marks] c) Based on your answer in part (b), show the actions, operations and D-frontier to expose the fault. [10 marks) Q2. Referring to Figure 2, find a sequence of test vectors that can expose line c stuck-at 0 and d stuck-at 0 with the minimum number of clock cycles using time-frame expansion model (one sequence of test vectors, but can expose both faults). Initial state for all lines is unknown (x). Show the time-frame expansion circuit and the analysis. [20 marks) A A D Q C d B D o CLK