Use LT spice to model the practical op-amp with the following design specifications

Design Specifications

Open loop Voltage Gain,	1 Mega
Common-mode input resistance at both input terminals,	7 M
Differential-mode input resistance,	20 M
Output resistance,	80
Common mode input capacitance at both input terminals,	9 pF
Differential mode input capacitance,	8 pF
Input offset voltage,	6 mV
Cutoff frequency with a single dominating pole,	15 Hz
Rail output voltage limit:	|Vcc-1| V
Input bias current	negligible

The Vcc is defined by the user where base on the max output voltage needed.

Please briefly explain how does each specification may affect the result.

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