USE Quartus II to write this

Consider a RAM with the following specification: i. It contains 256 entries ii. Each entry has 64 bits. ii. It has two ports. One port for read. The other for write. The top view of the RAM is shown below. Write En Read_Adr Read Data Write_Adr Write Data> Clock (a) Design the RAM using only LEs (or ALMs) by Verilog. Your design should use the behavior model. Simulate your circuits. Show the hardware resources consumed by your design from the compilation report. (b) Design the RAM using only embedded memory bits using MegaWizard Plug-In Manager by Verilog. Simulate your circuits. Show the hardware resources consumed by your design from the compilation report Consider a RAM with the following specification: i. It contains 256 entries ii. Each entry has 64 bits. ii. It has two ports. One port for read. The other for write. The top view of the RAM is shown below. Write En Read_Adr Read Data Write_Adr Write Data> Clock (a) Design the RAM using only LEs (or ALMs) by Verilog. Your design should use the behavior model. Simulate your circuits. Show the hardware resources consumed by your design from the compilation report. (b) Design the RAM using only embedded memory bits using MegaWizard Plug-In Manager by Verilog. Simulate your circuits. Show the hardware resources consumed by your design from the compilation report